One very difficult and completely new aspect of the proposed analog calorimeters is that the
electronics readout will be embedded inside the detector. This greatly reduces the electronics
noise by reducing the parasitic capacitance and minimizes the number of connections to the
outside, bringing only out one digital data line per 100 channels. Furthermore this design keeps
dead space to a minimum, thus minimizing the Molière radius and allowing more compact
showers which is essential for the particle flow algorithm.
This puts severe constraints on the front-end electronics which must handle large dynamic
range signals with extremely low electronics noise while operating at extremely low power,
through a scheme of pulsed power mode. Also digitization will be performed inside the frontend
chip to minimize the transmission of sensitive analog signals and preserve data integrity.
This results in a complex and sophisticated read-out ASIC, which will advance the state of the
art of calorimeter front-end electronics. This newly developed front-end ASIC would be
adapted to different detectors, e.g. the Si-detectors of the proposed ECAL or the SiPM photo
detectors for the proposed analogue HCAL. Two prototypes are foreseen in 0.35 μm SiGe
technology and several blocks have already been tested by the microelectronics groups in
CALICE. Then, a prototype of the final configuration could be fabricated to be integrated and
tested in the modules described in tasks A and B. This will also require the development of
prototype motherboards that are integrated inside the detector and hold these ASICs and the
silicon detector. They would be “stitchable” so that identical motherboards would be
assembled in a slab and used everywhere in the calorimeter for cost efficiency.
Depending on the application the chips will be integrated into different types of readout
boards. For the ECAL they will be inside the active area, for the HCAL they can either be
mounted very close to the active planes, or also be mounted inside the active area. The chip
will be designed as being highly configurable, so that it can be adapted to a wide range of
analogue HCAL readout systems.
The digital version of the hadronic calorimeter needs a much simpler read out, the signal from
a gaseous detector being kept in one or two bits. The idea for the one bit read out is to use
comparators and do the zero suppression and the formatting in FPGAs; a digital ASIC for this
purpose is also under consideration. These in turn will be read through a token ring. For the
prototype the number of pads will be few 100 000.